The present invention relates generally to a fractional dividing module and related calibration method.
In a traditional Integer-N PLL, if finer output frequency resolution is desired, one approach is to pre-divide the input clock in order to lower the reference clock frequency. Since the output frequency is an integer (N) times the input frequency, a slower reference clock results in a finer frequency resolution. Using this approach, the maximum achievable PLL bandwidth is reduced since the loop bandwidth should not greatly exceed 10% of the reference clock frequency. Lowering the loop bandwidth causes VCO (voltage-controlled oscillator) phase noises and layout area increase due to the larger capacitors sizes required in the loop filter. The other approach to achieve finer frequency resolution with an integer-N PLL is to increase the output frequency and then divide the resulting VCO output clock. The disadvantage of the approach is power consumption increases due to the higher clock rate.
Generally, an approach to derive finer output frequency resolution is to use a Fractional-N PLL. With this approach, the feedback divider is typically controlled by a delta-sigma modulator, and the average divisor provided by the feedback divider is utilized to obtain the desired (fractional) value. Using a delta-sigma modulator to control the feedback divider, the quantization noise induced by the modulator will be shaped such that it is placed mostly at higher frequencies. The quantization noise can then be attenuated by the PLL's low-pass characteristic as seen at its input. While the Fractional-N approach enables a higher reference clock rate thereby enabling a higher loop bandwidth as set by stability constraints, the filtering constraints imposed by quantization noise may still limit the loop bandwidth to an undesired level.
The quantization noise of the fractional-N PLL can be reduced by shrinking the quantization level of the feedback divider in the fractional-N PLL. For example, the quantization error is halved if the quantization level of the feedback divider is halved (e.g. from 1 to 0.5). Thus, a feedback divider with finer quantization level is at issue.